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U4083B
Low-Power Audio Amplifier for Telephone Applications
Description
The integrated circuit, U4083B, is a low-power audio amplifier for telephone loudspeakers. It has differential speaker outputs to maximize the output swing at low supply voltages. There is no need for coupler capacitors. The U4083B has an open loop gain of 80 dB whereas the closed loop gain is adjusted with two external resistors. A chip disable pin permits powering down and/or muting the input signal.
Features
D Wide operating voltage range: 2 to 16 V D Battery-powered application due to low quiescent supply current: 2.7 mA typical D Chip disable input to power down the integrated circuit D Low power-down quiescent current D Drives a wide range of speaker loads D Output power, Po = 250 mW @ RL = 32 W (speaker) D Low harmonic distortion (0.5% typical) D Wide gain range: 0 dB to 46 dB
Benefits
D Low number of external components D Low current consumption
Block Diagram / Application Circuit
75 k W 0.1mF Input Ci Ri 3 kW Rf 4 Vi FC1 3 1m F C1 5mF 50 kW - 2 125 kW 50 k W + Amp.2 Bias circuit 7 GND
Figure 1. Block diagram/ application circuit
VS 6 - + 4 kW 4 kW Amp.1 5 VO1
8 VO2 1 CD
C2 FC2
93 7781 e
Order Information
Extended Type Number U4083B-MFP U4083B-MFPG3 Package SO8 SO8 Remarks Tube Taped and reeled
Rev. A4, 06-Mar-01
1 (11)
U4083B
Pin Description
Pins 2 and 3: Filtering,power supply rejection CD 1 8 VO2 GND VS VO1
94 8022
FC2 FC1 Vi
2
7
3
6
Power supply rejection is provided by capacitors C1 and C2 at Pin 3 and Pin 2, respectively. C1 is dominant at high frequencies whereas C2 is dominant at low frequencies (figures 4 to 7). The values of C1 and C2 depend on the conditions of each application. For example, a linepowered speakerphone (telephone amplifier) will require more filtering than a system powered by regulated power supply. The amount of rejection is a function of the capacitors and the equivalent impedance at Pin 3 and Pin 2 (see electrical characteristic equivalent resistance, R). Apart from filtering, capacitors C1 and C2 also influence the turn-on time of the circuit at power-up since capacitors are charged up through the internal resistors (50 kW and 125 kW) as shown in the block diagram. Figure 1 shows turn-on time versus C2 at VS = 6 V, for two different C1 values. Turn-on time is 60% longer when VS = 3 V and 20% shorter when VS = 9 V. Turn-off time is less than 10 ms Pin 4: Amplifier input Vi Pin 5: Amplifier output 1 VO1 Pin 8: Amplifier output 2 VO2 There are two identical operational amplifiers. Amp.1 has an open-loop gain w 80 dB at 100 Hz (figure 2), whereas the closed-loop gain is set by external resistors, Rf and Ri (figure 3). The amplifier is unity gain stable, and has a unity gain frequency of approximately 1.5 MHz. A closed-loop gain of 46 dB is recommended for a frequency range of 300 to 3400 Hz (voice band). Amp.2 is internally set to a gain of -1.0 (0 dB). The outputs of both amplifiers are capable of sourcing and sinking a peak current of 200 mA. Output voltage swing is between 0.4 V and Vs - 1.3 V at maximum current (figures 18 and 19). The output dc offset voltage between Pins 5 and 8 (VO1 - VO2) is mainly a function of the feedback resistor, Rf, because the input offset voltage of the two amplifiers neutralize each other. Bias current of Amp. 1 which is constant with respect to Vs, however, flows out of Pin 4 (Vi) and through Rf, forcing V01 to shift negative by an amount equal to Rf IIB and VO2 positive to an equal amount. The output offset voltage specified in the electrical characteristics is measured with the feedback resistor (Rf = 75 kW) shown in typical application circuit. It takes into account bias current as well as internal offset voltages of the amplifiers.
4
Figure 2. Pinning
5
Pin 1 2 3 4 5 6 7 8
Symbol CD FC2 FC1 Vi VO1 VS GND VO2
Function Chip disable Filtering, power supply rejection Filtering, power supply rejection Amplifier input Amplifier output 1 Voltage supply Ground Amplifier output 2
Functional Description Including External Circuitry
Pin 1: Chip disable * digital input (CD) Pin 1 (chip disable) is used to power down the IC to conserve power or muting or both. Input impedance at Pin 1 is typically 90 kW. Logic 0 < 0.8 V IC enabled (normal operation) Logic 1 > 2 V IC disabled Figure 15 shows the power supply current diagram. The change in differential gain from normal operation to muted operation (muting) is more than 70 dB. Switching characteristics are as follows: turn-on time ton = 12 to 15 ms turn-off time toff v 2 ms They are independent of C1, C2 and VS. Voltages at Pins 2 and 3 are supplied from VS and therefore do not change when the U4083B is disabled. Outputs * VO1 (Pin 5) and VO2 (Pin 8) * turn to a high impedance condition by removing the signal from the speaker. When signals are applied from an external source to the outputs (disabled), they must not exceed the range between the supply voltage, VS, and ground.
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Rev. A4, 06-Mar-01
U4083B
Pin 6: Supply and power dissipation Power dissipation is shown in figures 8 to 10 for different loads. Distortion characteristics are given in figures 11 to 13. P totmax + T jmax - T amb R thJA The IC's operating range is defined by a peak operating load current of "200 mA (figures 8 to 13). It is further specified with respect to different loads (see figure 14). The left (ascending) portion of each of the three curves is defined by the power level at which 10% distortion occurs. The center flat portion of each curve is defined by the maximum output current capability of the integrated circuit. The right (descending) portion of each curve is defined by the maximum internal power dissipation of the IC at 25C. At higher ambient temperatures, the maximum load power must be reduced according to the above mentioned equation.
where Tjmax = Junction temperature = 140C Tamb = Ambient temperature RthJA = Thermal resistance, junction-ambient Power dissipated within the IC in a given application is found from the following equation: Ptot = (VS IS) + (IRMS VS ) - (RL IRMS2)
Layout Considerations
Normally, a snubber is not needed at the output of the IC, unlike many other audio amplifiers. However, the PC board layout, stray capacitances, and the manner in which the speaker wires are configured, may dictate otherwise. Generally, the speaker wires should be twisted tightly, and be not more than a few cm (or inches) in length.
IS is obtained from figure 15 IRMS is the RMS current at the load RL.
Absolute Maximum Ratings
Reference point Pin 7, Tamb = 25C unless otherwise specified. Parameters Supply voltage Pin 6 Voltages Pins 1, 2, 3 and 4 Disabled Pins 5 and 8 Output current Pins 5 and 8 Junction temperature Storage temperature range Ambient temperature range Power dissipation: Tamb = 60C SO8 Symbol VS Value -1.0 to +18 -1.0 to (VS +1.0) -1.0 to (VS +1.0) "250 +140 -55 to +150 -20 to +70 440 Unit V V V mA C C C mW
Tj Tstg Tamb Ptot
Thermal Resistance
Parameters Junction ambient SO8 Symbol RthJA Value 180 Unit K/W
Operation Recommendation
Parameters Supply voltage Pin 6 Load impedance Pins 5 to 8 Load current Differential gain (5.0 kHz bandwidth) Voltage @ CD Pin 1 Ambient temperature range Symbol VS RL IL DG VCD Tamb Value 2 to 16 8.0 to 100 "200 0 to 46 VS -20 to +70 Unit V W mA dB V C
Rev. A4, 06-Mar-01
3 (11)
U4083B
Electrical Characteristics
Tamb = +25C, reference point Pin 7, unless otherwise specified Parameters Test Conditions / Pins Amplifiers (AC Characteristics) Open-loop gain (Amp. 1, f < 100 Hz) Closed-loop gain (Amp. 2) VS = 6.0 V, f = 1.0 kHz, RL = 32 W Gain bandwidth product Output power Symbol Min. Typ. Max. Unit
GVOL1 GV2 GBW Po Po Po d d d PSRR PSRR PSRR GMUTE VO VO VO VOH VOL DVO -IIB R R
80 -0.35 55 250 400 0.5 0.5 0.6 50 12 52 >70 1.0 1.15 2.65 5.65 VS-1 0.16 1.25 1.0 0 1.5 +0.35
dB dB MHz mW
Total harmonic distortion (f = 1.0 kHz)
Power supply rejection ratio
VS = 3.0 V, RL = 16 W, d < 10% VS = 6.0 V, RL = 32 W, d < 10% VS = 12 V, RL = 100 W, d < 10% VS = 6.0 V, RL = 32 W, Po = 125 mW VS > 3.0 V, RL = 8 W, Po = 20 mW VS > 12 V, RL = 32 W, Po = 200 mW VS = 6.0 V, DVS = 3.0 V C1 = T, C2 = 0.01 mF C1 = 0.1 mF, C2 = 0, f = 1.0 kHz C1 = 1.0 mF, C2 = 5.0 mF, f = 1.0 kHz
%
dB
VS = 6.0 V, 1.0 kHz < f < 20 kHz, CD = 2.0 V Amplifiers (DC Characteristics) Output DC level at VO1, VS = 3.0 V, RL = 16 W VO2 VS = 6.0 V Rf = 75 kW VS = 12 V Output high level IO = - 75 mA, 2.0 V < VS < 16 V Output low level IO = 75 mA, 2.0 V < VS < 16 V Output DC offset voltage VS = 6.0 V, Rf = 75 kW, (VO1 - VO2) RL = 32 W Input bias current at Vi VS = 6.0 V Equivalent resistance at VS = 6.0 V Pin 3 Equivalent resistance at VS = 6.0 V Pin 2 Chip disable Pin 1 Input voltage * low Input voltage * high VS = VCD = 16 V Input resistance Power supply current VS = 3.0 V, RL = T, CD = 0.8 V VS = 16 V, RL = T, CD = 0.8 V VS = 3.0 V, RL = T, CD = 2.0 V
Muting
dB
V V V
-30 100 18
0 100 150 25
+30 200 220 40
mV nA kW kW
VIL VIH RCD IS IS IS
0.8 2.0 50 90 175 4.0 5.0 100
65
V V kW mA mA mA
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Rev. A4, 06-Mar-01
U4083B
Typical Temperature Performance
Tamb = -20 to +70C Function Input bias current at Vi Total harmonic distortion VS = 6.0 V, RL = 32 W, Po = 125 mW, f = 1.0 kHz Power supply current VS = 3.0 V, RL = T, CD = 0 V VS = 3.0 V, RL = T, CD = 2.0 V Typical Change "40 + 0.003 Units pA/ C %/ C
- 2.5 - 0.03
mA/ C mA/ C
360 300 240 t on ( ms ) 180 120 60 VS switching from 0 to +6V 0 0
94 7838 e
40 C1 = 5 mF Rf = 150 kW Ri = 6 kW Differential gain ( dB ) 32 Rf = 75 kW Ri = 3 kW 24
Input Ci 0.1 mF Amp 1 Outputs VO2 Amp 2 Ri VO1 Rf
16 8 0
1 mF
2
4
6 C2 ( mF )
8
10
93 7797 e
0
1
10
100
Frequency ( kHz )
Figure 1. Turn-on time vs. C1, C2 at power on
Figure 3. Differential gain vs. frequency
100 80
99.33 92.67 Phase ( Degrees ) PSSR ( dB )
60
C1w1 mF C1 = 0.1 mF C2 = 10 mF
Phase
50
G (dB )
60
86.00
40
40 Gain 20 0 0.1
94 7839 e
79.33
30 C1 = 0
72.67 66.00 1000
20 10 0.1
93 7798 e
1
10 f ( kHz )
100
1 f ( kHz )
10
100
Figure 2. Amplifier 1 - open-loop gain and phase
Figure 4. Power supply rejection vs. frequency
Rev. A4, 06-Mar-01
5 (11)
U4083B
60 50 PSRR ( dB ) Ptot ( mW ) C1 = 0.1 mF 40 C2 = 5 mF C1w1 mF 1200 1000 800 6V 600 400 20 3V C1 = 0 200 0 0.1
93 7799 e
VS = 12 V
RL = 8 W
30
10 1 f ( kHz ) 10 100
0
93 7802 e
30
60
90 PL ( mW )
120
150
180
Figure 5. Power supply rejection vs. frequency
60
Figure 8. Device dissipation
1200 V = 16 V S 1000
C1w5 mF C1 = 1 mF C2 = 1 mF C1 = 0.1 mF Ptot ( mW )
12 V RL = 16 W
50 PSSR ( dB )
800 600 400 6V
40
30 20 C1 = 0 10 0.1 1 f ( kHz ) 10 100
200 0 0
93 7803 e
3V
100
200 PL ( mW )
300
400
93 7800 e
Figure 6. Power supply rejection vs. frequency
55 C1w5 mF 45 PSSR ( dB ) 35 C1 = 1 mF C2 = 0 25 15 5 0.1
93 7801 e
Figure 9. Device dissipation
1200 VS = 16 V 1000 800 RL = 32 W 600 400 12 V
Ptot ( mW )
C1 = 0.1 mF 200 3V 0 1 f ( kHz ) 10 100
93 7804 e
6V
0
100
200
300 PL ( mW )
400
500
600
Figure 7. Power supply rejection vs. frequency
Figure 10. Device dissipation
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Rev. A4, 06-Mar-01
U4083B
10
94 7842 e
8
6 d(%)
VS = 3V RL = 16W
VS = 3V RL = 8W
f = 1 kHz DGV = 34dB
VS = 6V RL = 32W
4
2
VS = 16V RL = 32W
VS = 6V RL = 16W VS = 12V RL = 32W
0 0 100 200 PO ( mW ) 300
400
Figure 11. Distortion vs. power
10
94 7843 e
8
6 d(%)
VS = 3V RL = 16W
VS = 3V RL = 8W
f = 3 kHz DGV = 34dB
VS = 6V RL = 32W
4 VS = 6V RL = 16W 2 VS = 16V RL = 32W Limit
VS = 12V RL = 32W
0 0 100 200 PO ( mW ) 300 400
Figure 12. Distortion vs. power
Rev. A4, 06-Mar-01
7 (11)
U4083B
10
94 7844 e
8
6 d(%)
VS = 3V RL = 16W
VS = 3V RL = 8W
f = 1 or 3 kHz DGV = 12dB
VS = 6V RL = 32W
4
2 VS = 16V RL = 32W Limit 0 0 100 200 PO ( mW ) 300 VS = 6V RL = 16W Limit VS = 12V RL = 32W 400
Figure 13. Distortion vs. power
600 Tamb = 25C - Derate at higher temperature 500 400 PL ( W ) 300 200 100 0 0
93 7805 e
5 RL = R 4 CD = 0 IS ( mA ) 3
RL = 32 W
16 W
2 1 CD = VS 0 16 20
93 7806 e
8W
4
8
12 VS ( V )
0
4
8
12 VS ( V )
16
20
Figure 14. Maximum allowable load power
Figure 15. Power-supply current
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Rev. A4, 06-Mar-01
U4083B
1.3 Output 20mV/Div 1.2 V S -VOH ( V )
1.1
1.0 2VVS16V 0.9 0.8
Input 1mV/Div
93 7807 e
20 ms/Div
0
93 7809 e
40
80
120
160
200
IL ( mA )
Figure 16. Smal signal response
Figure 18. VS - VOH vs. load current
2.0
Output 1V/Div
1.6 VOL ( V )
1.2 VS = 2V 0.8 VS = 3V 0.4 VS 6V 0
Input 80mV/Div
93 7808 e
20 ms/Div
93 7810 e
0
40
80
120
160
200
IL ( mA )
Figure 17. Large signal response
Figure 19. VOL vs. load current
Rev. A4, 06-Mar-01
9 (11)
U4083B
Package Information
Package SO8
Dimensions in mm
5.00 4.85 1.4 0.4 1.27 3.81 8 5 0.25 0.10 0.2 3.8 6.15 5.85 5.2 4.8 3.7
technical drawings according to DIN specifications 13034
1
4
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Rev. A4, 06-Mar-01
U4083B
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.atmel-wm.com
Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
Rev. A4, 06-Mar-01
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